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Ordering number : ENN6171
CMOS IC
LC72344W, 72345W
Low-Voltage ETR Controller with On-Chip DC-DC Converter
Overview
The LC72344W and LC72345W are low-voltage electronic tuning microcontrollers that include a DC-DC converter, a PLL that operates up to 230 MHz, a 1/4 duty 1/2 bias LCD driver and other functions on chip. The built-in DC-DC converter provided by these ICs can easily implement a tuning system voltage generator circuit, and furthermore, since the transistor required for the low-pass filter is built in, these ICs can contribute to further end product cost reductions. Additionally, the DC-DC converter output voltage can be provided to other external ICs, making these products optimal for low-voltage portable audio equipment that includes a radio receiver.
Package Dimensions
unit: mm 3190-SQFP64
[LC72344W, 72345W]
12.0 10.0 1.25
48 49
0.5
0.18
1.25
33 32
0.15
12.0 10.0 0.5
1.25
64
17 1 16
Functions
* Program memory (ROM): 3072 x 16 bits (6 KB) LC72344W 4096 x 16 bits (8 KB) LC72345W * Data memory (RAM): 192 x 4 bits LC72344W 256 x 4 bits LC72345W * Cycle time: 40 s (all 1-word instructions) * Stack: 8 levels * LCD driver: 48 to 76 segments (1/4 duty, 1/2 bias drive) * Interrupts: One external interrupt Timer interrupts (1, 5, 10, and 50 ms) * A/D converter: Two input channels (5-bit successive approximation conversion) * Input ports: 6 ports (of which 2 can be switched for use as A/D converter inputs) * Output ports: 6 ports (of which 1 can be switched for use as the beep tone output and 2 are opendrain ports) * I/O ports: 16 ports (of which 8 can be switched for use as LCD ports as mask options)
(Continued on next page.)
0.5
0.1 0.5
1.7max
1.25
SANYO: SQFP64
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
31000RM (OT) No. 6171-1/13
LC72344W, 72345W
(Continued from preceding page.)
* PLL: Supports dead band control (two types) Reference frequencies: 1, 3, 5, 6.25, 12.5, and 25 kHz * Input frequencies: FM band: 10 to 230 MHz AM band: 0.5 to 10 MHz * Input sensitivity: FM band: 35 mV rms (50 mV rms at 130 MHz or higher frequency) AM band: 35 mV rms * External reset input: During CPU and PLL operation, instruction execution is started from location 0. * Built-in power-on reset circuit: The CPU starts executing from location 0 when power is first applied. * Static power-on function: Backup state clear function using the BATT pin. Pin Assignment
63 TEST1
* * * *
*
*
* * *
Halt mode: The controller operating clock is stopped. Backup mode: The crystal oscillator is stopped. Beep tone: 1.5 and 3.1 kHz Built-in DC-DC converter: Two systems (One system can be used as an external circuit power supply by providing an external transistor.) Built-in low-pass filter amplifier: An external low-pass filter amplifier circuit is no longer required in end products. Remaining power check function: The battery voltage can be directly converted to a digital value by the A/D converter. Memory retention voltage: 0.9 V or higher. VDD voltage: 0.9 to 1.8 V Package: SQFP-64 (0.5 mm lead pitch)
53 COM1
52 COM2
51 COM3
62 AGND
61 AOUT
59 EO
54 BRES
56 FMIN
58 VSS
55 VDD
64 XIN
60 AIN
50 COM4
57 AMIN
XOUT TEST2 PA3 PA2 PA1 PA0 PB3 PB2 PB1 PB0 PC3 PC2 PC1 PC0 PD3
49 S1 48 S2 47 S3 46 S4 45 S5 44 S6 43 S7 42 S8 41 S9 40 S10 39 S11 38 S12/PH0 37 S13/PH1 36 S14/PH2 35 S15/PH3 34 S16/PG0 33 S17/PG1 PG2/S18 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LC72344W LC72345W
PD2 16 PE1 19 20 21 24 25 27 28 29 30 VADJ 22 23 VSS 26 PD1 17 18 31 PG3/S19
BATT
VDC1
VDC3
VDC2
VREF
INT/PD0
ADI1/PF1
BEEP/PE0
ADI0/PF0
VCON
(Top view)
No. 6171-2/13
LC72344W, 72345W
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Symbol VDD(1)max Maximum supply voltage VDD(2)max VDD(3)max VDD(4)max Input voltage VIN(1) VIN(2) VOUT(1) Output voltage VOUT(2) VOUT(3) VOUT(4) IOUT(1) IOUT(2) Output current IOUT(3) IOUT(4) IOUT(5) Allowable power dissipation Operating temperature Storage temperature Pdmax Topr Tstg VDD VDC1 VDC2 VDC3 PF, FMIN, AMIN, AIN, BATT, and BRES PA, PC, PD, PG, and PH AOUT, and PE PB, PC, PD, PG, and PH VREF, and EO COM1 to COM4, S1 to S19 PC, PD, PG, PH, and EO PB AOUT, and PE S1 to S20 COM1 to COM4 Ta = -20 to +70C Conditions Ratings -0.3 to +0.3 -0.3 to +4.0 -0.3 to +4.0 -0.3 to +4.0 -0.3 to VDD(3) to +0.3 -0.3 to VDD(1) to +0.3 -0.3 to +15 -0.3 to VDD(1) +0.3 -0.3 to VDD(3) +0.3 -0.3 to VDD(4) +0.3 0 to 3 0 to 1 0 to 2 300 3 200 -20 to +70 -45 to +125 Unit V V V V V V V V V V mA mA mA A mA mW C C
Allowable Operating Ranges at Ta = -20 to +70C, VDD = 0.9 to 1.8 V
Parameter Symbol VDD(1) VDD(2) Supply voltage VDD(3) VDD(4) VDD(5) VIH(1) Input high-level voltage VIH(2) VIH(3) VIH(4) VIL(1) Input low-level voltage VIL(2) VIL(3) VIL(4) VIN(1) Input amplitude VIN(2) VIN(3) Input voltage range VIN(4) FIN(1) Input frequency FIN(2) FIN(3) FIN(4) Conditions The voltage applied to the VDD pin The voltage applied to the VDC1 pin The voltage applied to the VDC2 pin The voltage applied to the VDC3 pin Memory retention voltage Ports PC, PD, PG, and PH Port PA Port PF Ports BRES and BATT Ports PC, PD, PG, and PH Port PA Port PF Ports BRES and BATT XIN FMIN, AMIN: VDD(3) = 2.1 V FMIN: VDD(3) = 2.1 V CI 35 k ADI0, ADI1, and VDD XIN: FMIN: VIN(2), VDD(3) = 2.1 V FMIN: VIN(3), VDD(3) = 2.1 V AMIN(L): VIN(2), VDD(3) = 2.1 V Ratings min 0.9 0.9 1.8 2.6 0.9 0.7 VDD(1) 0.8 VDD(1) 0.8 VDD(1) 0.6 VDD(1) 0 0 0 0 0.5 0.035 0.05 0 70 10 130 0.5 75 VDD(1) VDD(1) VDD(3) VDD(3) 0.3 VDD(1) 0.2 VDD(1) 0.2 VDD(1) 0.2 VDD(1) 0.6 0.35 0.35 VDD(4) 80 130 230 10 typ 1.5 1.5 2.1 3.0 max 1.8 1.8 2.4 3.4 Unit V V V V V V V V V V V V V Vrms Vrms Vrms V kHz MHz MHz MHz
No. 6171-3/13
LC72344W, 72345W Electrical Characteristics under allowable operating conditions
Parameter Symbol IIH(1) IIH(2) Input high-level voltage IIH(3) IIH(4) IIL(1) IIL(2) Input low-level voltage IIL(3) IIL(4) Input floating voltage Pull-down resistor Hysteresis VIF RPD(1) RPD(2) VH VOH(1) VOH(2) Output high-level voltage VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) VOL(1) VOL(2) VOL(3) Output low-level voltage VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Output off leakage current A/D converter error Internal clock frequency fosc(1) fosc(2) IDD1(1) IDD2(2) IDD3(3) IDD1(4) Current drain IDD2(5) IDD3(6) IDD1(7) IDD2(8) IDD3(9) IOFF(1) IOFF(2) Conditions XIN: VDD(1) = 1.8 V, VDD(2) = 1.8 V, VDD(3) = 2.1 V FMIN, and AMIN: VDD(3) = 2.1 V Ports BRES, BATT, and PF: VDD(3) = 2.1 V Ports PA (no pull-down resistor), PC, PD, PG, and PH: VDD(1) = 1.8 V XIN: VDD(1) = VDD(2) = VDD(3) = VSS FMIN, and AMIN: VDD(3) = VSS Ports BRES, BATT, and PF: VDD(3) = VSS Ports PA (no pull-down resistor), PC, PD, PG, and PH: VDD(1) = VSS Port PA pull-down resistor present Port PA pull-down resistor: VDD(1) = 1.3 V TEST1 and TEST2 pull-down resistors BRES PB: IO = 1 mA PC, PD, PG, PH: IO = 1 mA EO: IO = -500 A XOUT IO = 1 A S1 to S20: IO = 20 A COM1, CM2, COM3, and COM4: IO = 100 A VREF: IO = 1 mA PB: IO = -50 A PC, PD, PG, and PH: IO = -1 mA EO: IO = -500 A XOUT: IO = -1 A S1 to S20: IO = -20 A COM1, COM2, COM3, and COM4: IO = -100 A PE: IO = 2 mA AOUT: IO = 1 mA, AIN = 1.3 V: VDD(4) = 3 V PB, PC, PD, PG, PH, and E0 ports AOUT and PE ports ADI0 and ADI1, VDD FM, and PLLSTOP: VDD(3) = 2.1 V, Vcon = OPEN AM VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: FIN(2) 130 MHz, Ta = 25C VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: FIN(2) 130 MHz, Ta = 25C VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: FIN(2) 130 MHz, Ta = 25C VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: Halt mode, Ta = 25C *1 VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: Halt mode, Ta = 25C *1 VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: Halt mode, Ta = 25C *1 VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: With the oscillator stopped, Ta = 25C * VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: With the oscillator stopped, Ta = 25C * VDD(1) = 1.5 V, VDD(3) = 2.1 V, VDD(4) = 3.0 V: With the oscillator stopped, Ta = 25C * -3 -100 -1/2 300 450 1 5 1 0.1 0.3 0.1 100 500 100 600 75 100 10 0.1 VDD(3) 0.2 VDD(3) VDD(1) - 0.7 VDD(1) VDD(1) - 0.3 VDD(1) VDD(3) - 0.3 VDD(3) VDD(3) - 0.3 VDD(3) VDD(4) - 1 VDD(4) - 1 VDD(3) - 1 0.3 VDD(1) 0.7 VDD(1) 0.3 VDD(1) 0.3 VDD(3) 0.3 VDD(3) VDD(4)-2 VDD(4)-2 0.6 VDD(1) 0.5 3 100 +1/2 900 1200 VDD(1) - 0.3 VDD(1) -3 -8 3 8 Ratings min typ max 3 20 4 3 -3 -20 -4 -3 0.05 VDD(1) 200 Unit A A A A A A A A V k k V V V V V V V V V V V V V V V V A nA LSB kHz kHz mA mA mA mA mA mA nA nA nA
The halt mode current drain is due to 20 instructions being executed every 125 ms.
No. 6171-4/13
LC72344W, 72345W
*1 Halt mode current drain test conditions IDD1 A
*2 Backup mode current drain test conditions IDD1 A
7 pF
1.5 V
7 pF
1.5 V
75 kHz XOUT XIN 7 pF PA,PF AIN VSS FMIN AMIN AGND TEST1, 2 BATT VDC3 VDD RES VDC2 IDD2 A A IDD3 2.2 V 3V
75 kHz XOUT XIN 7 pF AIN VSS FMIN AMIN AGND TEST1, 2 BATT VDD RES VDC2 VDC3 IDD2 A A IDD3 2.2 V 3V
Leave all ports other than those mentioned above open. Select output mode for PC and PD. Select the segment function for S12 to S19.
Leave all ports other than those mentioned above open. Select output mode for PC and PD. Select the segment function for S12 to S19.
No. 6171-5/13
LC72344W, 72345W Block Diagram
XIN XOUT FMIN
DIVIDER SYSTEM CLOCK GENERATOR 1/2 1/16,1/17
REFERENCE DIVIDER
PHASE DETECTOR
EO
PROGRAMMBLE DIVIDER
AMIN 1/2 PLL DATA LATCH 1/2 VSS 1/2 TIME BASE CONTROL UNIVERSAL COUNTER (20 bits) RES * P-ON RESET TEST1 TEST2 PA0 PA1 PA2 PA3 ROM PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3 INT/PD0 PD1 PD2 PD3 AIN AOUT AGND VDC3 VDC1 VDC2 VCON VREF VADJ TIMER 0 MPX (5 bits) MPX LATCH B LATCH A ALU * DATA LATCH / BUS DRIVER DATA LATCH / BUS DRIVER DATA LATCH / BUS DRIVER 3k x 16 bits (LC72344) 4k x 16 bits (LC72345) INSTRUCTION DECODER SKIP JMP CAL RETURN INTERRUPT RESET BANK CF COMMON DRIVER COM4 COM3 COM2 COM1 BEEP TONE DATA LATCH / BUS DRIVER PE0/BEEP MPX PE0/BEEP BUS DRIVER BUS CONTROL RAM 192 x 4 bits (LC72344) 256 x 4 bits (LC72345) ADDRESS DECODER BANK DATA LATCH / BUS DRIVER DATA LATCH / BUS DRIVER S11 COUNT END SEG 7 LA LCD PORT DRIVER PLL CONTROL LCDA/B
S1
4
80
LCPA/B
S12/PH3 S13/PH2 S14/PH1 S15/PH0 S16/PG3 S17/PG2 S18/PG1 S19/PG0
ADDRESS DECORDER 14 ADDRESS COUNTER 14 STACK
JUDGE
VDD
DATA LATCH / BUS DRIVER RC OSCILLATOR CIRCUIT
PF0/ADI0 PF1/ADI1 BATT
DATA BUS
No. 6171-6/13
LC72344W, 72345W Pin Functions
Pin No. Pin I/O Function I/O circuit
64 1
XIN XOUT
I O
75 kHz crystal oscillator connections
63 2
TEST1 TEST2
I I
IC testing. These pins must be connected to ground.
--
6 5 4 3
PA0 PA1 PA2 PA3 I
Special-purpose ports for key return signal input designed with a low threshold voltage. When a key matrix is formed in combination with port PB, simultaneous multiple key presses with up to 3 keys can be detected. The pull-down resistors are set up for all four pins at the same time with the IOS instruction (PWn = 2.b1). This setting cannot be specified for individual pins. In backup mode, these pins go to the input disabled state, and the pull-down resistors are disabled after a reset.
Input with built-in pull-down resistor
Unbalanced CMOS push-pull output 10 9 8 7 PB0 PB1 PB2 PB3 O Unbalanced CMOS outputs. These outputs are switched with the IOS 0 instruction. Since these outputs are unbalanced, no diodes are required to prevent short circuits due to simultaneous multiple key presses. These outputs go to the high-impedance output state in backup mode. After a reset, they go to the high-impedance output state and remain in that state until an output instruction (OUT, SPB, or RPB) is executed.
14 13 12 11
PC0 PC1 PC2 PC3 I/O General-purpose I/O ports. PD0 can be used as an external interrupt port. The IOS instruction (Pwn = 4, 5) is used for switching the general-purpose I/O port function, and these ports can be set to input or output in 1-bit units. (0: input, 1: output) In backup mode they go to the input disabled high-impedance state. After a reset, they switch to the general-purpose input port function.
CMOS push-pull output
18 17 16 15
INT/PD0 PD1 PD2 PD3 (*)
General-purpose output and beep tone output shared function ports (PE0 only). The BEEP instruction is used to switch PE0 between the general-purpose output port and beep tone output functions. To use PE0 as a general-purpose output port, execute a BEEP instruction N-channel open-drain output with b2 set to 0. Set b2 to 1 to use PE0 as the beep tone output port. The b0 and b1 bits are used to select the beep tone frequency. There are two beep tone frequencies supported. 20 19 BEEP/PE0 PE1 *: When PE0 is set up as the beep tone output, executing an output instruction to PN0 only changes the state of the internal output latch, it does not affect the beep tone output in any way. Only the PE0 pin can be switched between the general-purpose output function and the beep tone output function; the PE1 pin only functions as a general-purpose output. These pins go to the high-impedance state in backup mode and remain in that state until an output instruction or a BEEP instruction is executed. Since these ports are open-drain ports, resistors must be inserted between these pins and VDD. These ports are set to their generalpurpose output port function after a reset.
Continued on next page.
No. 6171-7/13
LC72344W, 72345W
Continued from preceding page.
Pin No. Pin I/O Function General-purpose input and A/D converter input shared function ports. The IOS instruction (Pwn = FH) is used to switch between the general-purpose input and A/D converter port functions. The general-purpose input and A/D converter port functions can be switched in a bit units, with 0 specifying general-purpose input, and 1 specifying the A/D converter input function. To select the A/D converter function, set up the A/D converter pin with an IOS instruction with Pwn set to 1. The A/D converter is started with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is set when the conversion completes. The INR instruction is used to read in the data. *: If an input instruction is executed for one of these pins which is set up for analog input, the read in data will be at the low level since CMOS input is disabled. In backup mode these pins go to the input disabled high-impedance state. These ports are set to their general-purpose input port function after a reset. The A/D converter is a 5-bit successive approximation type converter, and features a conversion time of 1.28 ms. Note that the full-scale A/D converter voltage (1FH) is (63/96) times VDC3. LCD driver segment output and general-purpose I/O shared function ports. The IOS instruction* is used for switching both between the segment output and generalpurpose I/O functions and between input and output for the general-purpose I/O port function. * When used as segment output ports 31 32 33 34 PG3/S19 PG2/S18 PG1/S17 PG0/S16 O The general-purpose I/O port function is selected with the IOS instruction (Pwn = 8). b0 = S16 to 19/PG0 to 3 (0: Segment output, 1: PG0 to 3) The general-purpose I/O port function is selected with the IOS instruction (Pwn = 9). b0 = S12 to 15/PH0 to 3 (0: Segment output, 1: PH0 to 3) * When used as general-purpose I/O ports 35 36 37 38 PH3/S15 PH2/S14 PH1/S13 PH0/S12 (*) The IOS instruction (Pwn = 6,7) is used to select input or output. Note that the mode can be set in a bit units. b0 = PG0 b1 = PG1 b2 = PG2 b3 = PG3 CMOS push-pull output CMOS input/analog input I/O circuit
23 22
PF0/ADI0 PF1/ADI1
I
(
0: Input 1: Output
)
b0 = PH0 b1 = PH1 b2 = PH2 b3 = PH3
(
0: Input 1: Output
)
In backup mode, these pins go to the input disabled high-impedance state if set up as general-purpose outputs, and are fixed at the low level if set up as segment outputs. These ports are set up as segment outputs after a reset. Although the general-purpose port/LCD port setting is a mask option, the IOS instruction must be used as described above to set up the port function.
CMOS push-pull output LCD driver segment output pins. A 1/4-duty 1/2-bias drive technique is used. 39 to 49 S11 to S1 O The frame frequency is 75 Hz. In backup mode, these outputs are fixed at the low level. After a reset, these outputs are fixed at the low level.
50 51 52 53
COM4 COM3 COM2 COM1 O
LCD driver common output pins. A 1/4-duty 1/2-bias drive technique is used. The frame frequency is 75 Hz. In backup mode, these outputs are fixed at the low level. After a reset, these outputs are fixed at the low level.
System reset input. 54 RES I In CPU operating mode or halt mode, applications must apply a low level for at least one full machine cycle to reset the system and restart execution with the PC set to location 0. This pin is connected in parallel with the internal power on reset circuit. Battery presence/absence discrimination. The internal clock oscillator starts when a high level is input to this pin. The IN instruction can be used to determine whether or not a battery is present.
21
BATT
I
Continued on next page. No. 6171-8/13
LC72344W, 72345W
Continued from preceding page.
Pin No. 24 Pin VDC1 I/O I VDC3 (3 V) step-up control. 2.1 V power supply. Apply either the voltage stepped-up by the DC-DC converter or an equivalent voltage (2.1 V typical). 3 V power supply. Apply either the voltage stepped-up by VDC1 or an equivalent voltage (3 V typical). VDC2 step-up transistor drive. Frequency adjustment for the internal RC oscillator circuit. The RC oscillator frequency can be lowered by inserting a capacitor between this pin and ground. The VDC3 voltage can be adjusted by inserting a resistor between this pin and ground. CMOS amplifier input FM VCO (local oscillator) input. 56 FMIN I This pin is selected with the PLL instruction CW1. The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. Function I/O circuit
27
VDC2
I
25
VDC3
I
28
VREF
O
29
VCON
I
30
VADJ
O
AM VCO (local oscillator) input. This pin and the bandwidth are selected with the PLL instruction CW1. CW1 b1, b0 57 AMIN I 11 Bandwidth 0.5 to 10 MHz (MW, LW)
CMOS amplifier input
The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. CMOS push-pull output Main charge pump output. When the local oscillator frequency divided by N is higher than the reference frequency a high level is output, when lower, a low level is output, and the pin is set to the high-impedance state when the frequencies match. This output goes to the high-impedance state in backup mode, in halt mode, after a reset, and in PLL stop mode.
59
EO
O
60 61 62
AIN AOUT AGND O
Transistor used for the low-pass filter amplifier. Connect AGND to ground.
Power supply pin. 26 58 55 VSS VSS VDD -- This pin must be connected to ground. This pin must be connected to ground. This pin must be connected to VDD. Supports A/D converter. --
Note: *Applications must establish the output data in advance with an OUT, SPB, or RPB instruction and then set the pin to output mode with an IOS instruction when using the I/O switchable ports as output pins.
No. 6171-9/13
LC72344W, 72345W DC-DC Converter Application Sample
VDC3 3 V system comparator + VDC1
LCD, A/D converter, and power reset
TU+B VDC2
Internal power supply
VADJ 2.1 V system comparator VREF + Reference voltage
FM mode VCON RC oscillator
AM mode Local AM signal
IC internal circuits
VDD Supply voltage (0.9 to 1.8 V)
Low-Pass Filter Application Sample
EO
IC internal circuits
AIN
Varactor
AOUT
TU+B AGND
No. 6171-10/13
LC72344W, 72345W LC72344W and LC72345W Instruction Set Terminology ADDR b C DH DL I M N Rn Pn PW r ( ), [ ] M (DH, DL) : Program memory address : Borrow : Carry : Data memory address High (Row address) [2 bits] : Data memory address Low (Column address) [4 bits] : Immediate data [4 bits] : Data memory address : Bit position [4 bits] : Resister number [4 bits] : Port number [4 bits] : Port control word number [4 bits] : General register (One of the address from 00H to 0FH of BANKO) : Contents of register or memory : Data memory specified by DH, DL
Instruction group
Mnemonic AD ADS
Operand 1st r r r r M M M M r r r r M M M M 2nd M M M M I I I I M M M M I I I I Add M to r
Function
Operational function r (r) + (M) r (r) + (M), skip if carry r (r) + (M) + C r (r) + (M) + C skip if carry M (M) + I M (M) + I, skip if carry M (M) + I + C M (M) + I + C, skip if carry r (r) - (M) r (r) - (M), skip if borrow r (r) - (M) - b r (r) - (M) - b, skip if borrow M (M) - I M (M) - I, skip if borrow M (M) - I - b M (M) - I - b, skip if borrow
Instruction format f 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 e 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 d 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 c 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 a 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 9 8 7 6 5 4 3 2 r r r r I I I I r r r r I I I I 1 0
DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH
DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL
Add M to r, then skip if carry Add M to r with carry Add M to r with carry, then skip if carry Add I to M Add I to M, then skip if carry Add I to M with carry Add I to M with carry, then skip if carry Subtract M from r Subtract M from r, then skip if borrow Subtract M from r with borrow Subtract M from r with borrow, then skip if borrow Subtract I from M Subract I from M, then skip if borrow Subtract I from M with borrow Subtract I from M with borrow, then skip if borrow
Addition instructions
AC ACS AI AIS AIC AICS SU SUS
Subtraction instructions
SB SBS SI SIS SIB SIBS
Continued on next page.
No. 6171-11/13
LC72344W, 72345W
Continued from preceding page.
Instruction group
Mnemonic SEQ SEQI SNEI SGE SGEI SLEI
Operand 1st r M M r M M r M r M r M r r M r M M1 M M M M r M r M2 I N N 2nd M I I M I I M I M I M I
Function Skip if r equal to M Skip if M equal to I Skip if M not equal to I Skip if r is greater than or equal to M Skip if M is greater than equal to I Skip if M is less than I AND M with r AND I with M OR M with r OR I with M Exclusive OR M with r Exclusive OR M with M Shift r right with carry Load M to r Store r to M Move M to destination M referring to r in the same row Move source M referring to r to M in the same row Move M to M in the same row Move I to M Test M bits, then skip if all bits specified are true Test M bits, then skip if all bits specified are false Jump to the address Call subroutine Return from subroutine Return from interrupt
Operational function (r) - (M), skip if zero (M) - I, skip if zero (M) - I, skip if not zero (r) - (M), skip if not borrow (M) - I, skip if not borrow (M) - I, skip if borrow r (r) AND (M) M (M) AND I r (r) OR (M) M (M) OR I r (r) XOR (M) M (M) XOR I carry (r) r (M) M (r) [DH, Rn] (M) M [DH, Rn] [DH, DL1] [DH, DL2] MI
Instruction format f 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 e 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 d 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 c 1 1 0 1 1 0 0 0 0 0 1 1 0 1 1 1 1 0 0 1 1 b 0 1 0 1 1 1 0 0 1 1 0 1 0 0 0 1 1 0 0 0 0 a 0 0 1 0 1 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 9 8 7 6 5 4 3 2 r I I r I I r I r I r I 0 r r r r r DL2 I N N 1 0
Comparison instruction
DH DH DH DH DH DH DH DH DH DH DH DH 0 0 1
DL DL DL DL DL DL DL DL DL DL DL DL 1 1
Logical operation instructions
AND ANDI OR ORI EXL EXLI SHR LD
DH DH DH DH DH DH DH DH
DL DL DL DL DL1 DL DL DL
Transfer instructions
ST MVRD MVRS MVSR MVI
Bit test instructions
TMT TMF JMP CAL RT RTI
if M (N) = all 1s, then skip 1 if M (N) = all 0s, then skip 1 PC ADDR PC ADDR Stack (PC) + 1 PC Stack PC Stack, BANK Stack, CARRY Stack 1 1 0 0
Jump and subroutine instructions
ADDR ADDR
ADDR (13 bits) ADDR (13 bits) 0 0 1 1 0 0 0 0 0 1
No. 6171-12/13
LC72344W, LC72345W
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of March, 2000. Specifications and information herein are subject to change without notice. PS No. 6171-13/13

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